Since the introduction of semiconductor devices, the size of semiconductor devices has been continuously shrinking, resulting in smaller semiconductor chip size and increased device density. One of the difficult factors in the continuing evolution toward smaller device size and higher density has been the ability to consistently form small critical dimensions within predetermined error windows. For example, semiconductor feature sizes are frequently subjected to optical or electrical metrology inspections following photolithographic patterning and etching to ensure that critical dimensions are within acceptable limits. In addition, the reliability and continuity of integrated circuitry, for example formed by damascene manufacturing methods, is checked by electrical resistance methods following a manufacturing step. Generally, the electrical integrity of micro-integrated circuitry has been determined by resistance or current testing where automated voltage or current test probes are applied to selected portions of the semiconductor device to sequentially check portions of the circuitry for electrical continuity of the circuitry wiring also referred to as electrical interconnects.
One technique that has been gaining popularity is the use of the scanning electron microscope (SEM) to monitor the current induced by impacting the primary electron beam onto semiconductor features. For example, in a conventional SEM imaging technique a beam of electrons is focused and accelerated onto a small portion of the sample where the impacting electrons create secondary electrons within the sample, of which a portion escape and are emitted into a sub-atmospheric specimen chamber where they are collected into an electron detector to produce a current or voltage which is then processed for imaging the sample. The SEM is superior to optical techniques in that the resolution is orders of magnitude higher, for example in the range of hundreds of Angstroms or less.
In a typical SEM system, a focused electron beam is scanned from point to point on a specimen surface in a rectangular raster pattern. Several variables including accelerating electron beam voltage, electron beam current, and electron beam spot size may be optimized depending on the sample material and the desired magnification.
A typical SEM accelerates and magnetically focuses a beam of electrons having energies typically in the kilovolt range for producing an image from secondary electrons. The brightness or darkness of the processed image depends on the relative amount of detected secondary electrons emitted from the sample which in turn partially depends on the accelerating voltage and the work function of the sample material as well as the topography of the sample. The work function of the sample material additionally defines the electron current that is induced within the sample from impacting primary beam electrons.
In the context of circuit continuity analysis, the SEM has been used to induce voltage, current, or capacitive changes in IC samples by the focused electron beam and measure the magnitude of the voltage changes. Among some of the electron beam methods that have been used for IC failure analysis include capacitive coupling voltage contrast (CCVC), electron beam induced current (EBIC), biased resistive contrast imaging (BRCI), and charge-induced voltage alteration (CIVA).
The CCVC method uses a changing voltage applied to a buried electrical conductor in the IC to produce a change in the secondary electron emission of an incident low-energy electron beam on the device surface of the IC. The EBIC method has been used to identify defects in the device layer of an IC by generating an electron-hole current in semiconductor junctions in the IC. A disadvantage of the EBIC methods of the prior art is that for ICs having overlying layers, the primary electron beam must have sufficient energy to penetrate through the passivation layer to reach the semiconductor device layer in the IC to create a detectable current on the order of about 1 micro-amp. In the BRCI method the sample image is generated by monitoring small fluctuations in the power supply current of an IC as an electron beam is scanned over the IC device surface. In the CIVA method the sample image is generated by monitoring the voltage shifts in a constant-current power supply as a relatively high-energy electron beam (about 5,000 eV or more for a passivated IC) is scanned over a biased IC.
One problem with prior art methods including measuring electron beam induced currents is that a relatively long signal carrying lead is required to transport the signal from the sample to ex-situ measuring devices. For example the sensitivity is generally limited by a signal to noise ratio which effectively limits the detected current sensitivity to about 1 micro-amp. The limited sensitivity of prior art methods creates the need for high energy electron beams to create sufficient current signals which can cause dielectric breakdown and associated electron beam induced damage to the sample, for example by in-situ X-ray generation. In addition, as electron accelerating voltages increase, the signal to noise ratio decreases. Further, as IC metal interconnects become smaller, the interconnect resistance increases, reducing the measurable electron beam induced current for a given electron accelerating voltage.
There is therefore a need in the semiconductor manufacturing art to develop an improved method and apparatus for sampling electron beam induced currents in IC semiconductor devices to increase sample current detection sensitivity to provide more reliable and sensitive measurements for conducting integrated circuitry failure analysis.
It is therefore an object of the invention to provide an improved method and apparatus for sampling electron beam induced currents in IC semiconductor devices to increase sample current detection sensitivity to provide more reliable and sensitive measurements for conducting integrated circuitry failure analysis while overcoming-other shortcomings of the prior art.